Quad data rate

Quad data rate (QDR, or quad pumping) is a communication signaling technique wherein data are transmitted at four points in the clock cycle: on the rising and falling edges, and at two intermediate points between them.

The effect is to deliver four bits of data per signal line per clock cycle.

This technology has allowed Intel to produce chipsets and processors that can communicate with each other at data rates expected of the traditional front-side bus (FSB) technology running from 400 MT/s to 1600 MT/s, while maintaining a lower and thus more stable actual clock frequency of 100 MHz to 400 MHz.

On a modern computer, there may be several CPUs and several I/O devices, all competing for accesses to the memory.

To handle this contention properly, modern systems aim to enable signals to propagate between all connected components within a single clock cycle, while setting a firm limit on the maximum clock rate.