Given enough AND gates, the time to produce the summands will be one cycle of the arithmetic logic unit.
The summands are reduced using a common 1-bit full adder that accepts two 1-bit terms and a carry-in bit.
The full adders are arranged such that the sum remains in the same column of summands, but the carry-out is shifted left.
In each row, the top three bits are the three inputs to the full adder (two terms and carry-in).
For design, it is important to note that rows 1, 3, 5, ... (counting from the top) are filled with sums from the column itself.
A basic full adder normally requires three cycles of the arithmetic logic unit.