SerDes

A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output.

The primary use of a SerDes is to provide data transmission over a single line or a differential pair in order to minimize the number of I/O pins and interconnects.

It may use an internal or external phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency.

Implementations may also make use of a double-buffered register to avoid metastability when transferring data between clock domains.

One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side.

This supports DC-balance, provides framing, and guarantees frequent transitions, allowing a receiver to extract the embedded clock.

The transmit side comprises a 64b/66b encoder, a scrambler, and a gearbox that converts the 66b signal to a 16-bit interface.

These IAs have been adopted or adapted or have influenced high speed electrical interfaces defined by IEEE 802.3, Infiniband, RapidIO, Fibre Channel and numerous others.