It is also impractical to manufacture a single chip with more than two DDR memory buses (channels).
The obvious solution is to use a narrower, higher-speed bus to interface to memory, and to implement it as a point-to-point link, daisy-chaining additional modules.
However, Intel have made two attempts at this, neither hugely successful: AMD's answer to this is the G3MX chip.
It can connect to multiple DIMMs but, to minimize latency, is not designed to be daisy-chained.
The G3MX has an asymmetrical link to the processor, to match typical memory usage patterns.