In CPU design, the use of a sum-addressed decoder (SAD) or sum-addressed memory (SAM) decoder is a method of reducing the latency of the CPU cache access and address calculation (base + offset).
The rest of this page assumes an instruction set architecture (ISA) with a single addressing mode (register+offset), a virtually indexed data cache, and sign-extending loads that may be variable-width.
For this example, a direct-mapped 16 KB data cache which returns doubleword (8-byte) aligned values is assumed.
The sum-addressed SRAM idea applies equally well to set associative caches.
One word line is driven high in response to each unique Addr[13:3] value.
The function for line 1026 would be: Both the carry chain of the adder and the decoder combine information from the entire width of the index portion of the address.
A sum-addressed SRAM combines the information just once by implementing the adder and decoder together in one structure.
However, the LSBs of the two summands can't be ignored because they may produce a carry-out which would change the doubleword addressed.
If R[13:3] and O[13:3] are added to get some index I[13:3], then the actual address Addr[13:3] is equal to either I[13:3], or I[13:3] + 1, depending on whether R[2:0]+O[2:0] generates a carry-out.
The two conditions can be written as: Ignore the last digit of the compare: (S+C)[13:4]==11..1 Similarly, the even SRAM bank fetches line Le==2N when either I[13:3]==2N or I[13:3]==2N-1.
It is possible to partially specialize the full adders to 2-input AND, OR, XOR, and XNOR because the L input is constant.
For our example cache subsystem, the critical path would be a 14-bit adder, producing true and complement values, followed by an 11-bit AND gate for each row of the decoder.
In the sum-addressed design, the final AND gate in the decoder remains, although 10 bits wide instead of 11.
United States patent 5,754,819, May 19, 1998, Low-latency memory indexing method and structure.
Inventors: Lynch; William L. (Palo Alto, CA), Lauterbach; Gary R. (Los Altos, CA); Assignee: Sun Microsystems, Inc. (Mountain View, CA), Filed: July 28, 1994 Evaluation of A + B = K Conditions without Carry Propagation (1992) Jordi Cortadella, Jose M. Llaberia IEEE Transactions on Computers, [1] [2] United States Patent 5,619,664, Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms, awarded April 18, 1997, Inventor: Glew; Andrew F. (Hillsboro, OR); Assignee: Intel Corporation (Santa Clara, CA), Appl.