Synchronous Data Link Control (SDLC) is a computer serial communications protocol first introduced by IBM as part of its Systems Network Architecture (SNA).
[7] Intel used SDLC as a base protocol for BITBUS, still popular in Europe as fieldbus and included support in several controllers (i8044/i8344, i80152).
Other vendors putting hardware support for SDLC (and the slightly different HDLC) into communication controller chips of the 1980s included Zilog, Motorola, and National Semiconductor.
Each secondary is responsible for copying all frames which arrive at its input so that they reach the rest of the ring and eventually return to the primary.
When powering on, a secondary waits for an opportune moment and then goes "on-loop" inserting itself into the data stream with a one-bit delay.
In SDLC loop mode, frames arrive in a group, ending (after the final flag) with an all-ones idle signal.
The first seven 1-bits of this (the pattern 01111111) constitute a "go-ahead" sequence (also called EOP, end of poll) giving a secondary permission to transmit.
After its own final flag, it transmits an all-ones idle signal, which will serve as a go-ahead for the next station on the loop.