Conte realized in the early 1990s that Flynn's prediction of the fetch bandwidth being the limit to increasing instruction-level parallelism was coming true.
His oft-cited International Symposium on Computer Architecture paper and subsequent work on instruction fetch mechanisms have influenced industry and spawned much follow-on research.
The work is of great interest to industry design teams who are struggling with performance limitations imposed by the speed gap between microprocessors and memory systems.
This work has major implications on the long-term viability of the EPIC architecture proposed in Intel Itanium processor family.
He was the first to realize that the limit to profile-driven optimization wasn't the technology itself, but it was the slowdown due to profiling that prevented its adoption by industry.
He and his students devised clever techniques to extract profile information from branch predictors on Intel Pentium processor.
The results are reflected in the performance counters that are present in the Intel Itanium, co-designed by one of Conte's Ph.D. students (Kishore Menezes).
The technique can produce performance similar to Scott Mahlke's hyperblock scheduling, but without needing predication support in the hardware.
In recognition of the changing landscape of the electronics and computer industries, Conte and Gargini renamed the effort the International Roadmap for Devices and Systems.