Vortex86

Before adopting the Vortex86 series, DM&P manufactured the ALi M6117D, which contains VM Technology VMT386SX+ derived x86 core, an Intel 386SX compatible, 25–40 MHz SoC.

Linux systems intended to run on i686 are generally not compatible with these Vortex86 models because the GNU C Library, when built for i686, uses a CMOV instruction in its assembly language strcmp function, which its dynamic loader (ld.so) uses.

[11] The CPU core is derived from the Rise mP6, which has three integer and MMX pipelines and branch prediction.

[12] Introduced in February 2007,[13] the Vortex86SX is an x86-compatible System-on-chip (SoC) with built-in north and south bridge on a 0.13 micron process in a 27x27 mm 581-pad BGA package.

The SoC adds the ability to function as a USB 1.1 client on 1 port and increases the embedded flash capacity to 2 MB.

The PDX-600 is a version of the Vortex86DX that differs only in the number of RS-232 ports (three instead of five) and has no I²C and servo controllers, thus targeting more the embedded than the industrial market.

[21] The CPU core improves on the DX by adding branch prediction, cache-access optimisation[22] and MMX instructions.

The SoC drops ISA bus attachment but adds a VGA-compatible 2D GPU, with separate DDR2 memory, and a HD Audio controller.

[29][30] It has an eight-way 32K I-Cache, an eight-way 32K D-Cache, a four-way 512 KB L2 cache with a write-through or write-back policy, ability to use up to 2 GB of DDR3 RAM, a PCI-e bus interface, 100 Mbit/s Ethernet, FIFO UART, a USB 2.0 host, integrated GPU, an ATA controller at Primary Channel, and a SATA 1.5 Gbit/s controller (one port) at Secondary Channel.

[32] The master core runs at 600 MHz, has 16K I-Cache, 16K D-Cache, and four-way 128 KB L2 cache with a write-through or write-back policy.

Both have a built-in FPU, as well as the MMX, cmpxchg8b and cmov instructions, but only the master core has SSE, SSE2, SSE3, SSSE3 and NX support [33].