Wafer-scale integration

In the normal integrated circuit manufacturing process, a single large cylindrical crystal (boule) of silicon is produced and then cut into disks known as wafers.

After all the possible locations are patterned, the wafer surface appears like a sheet of graph paper, with grid lines delineating the individual chips.

Those locations that are found to be defective are recorded and marked with a dot of paint (this process is referred to as "inking a die" and more modern wafer fabrication techniques no longer require physical markings to identify defective die).

Flaws on the surface of the wafers and problems during the layering/depositing process are impossible to avoid, and cause some of the individual chips to be defective.

Generally, this approach uses a grid pattern of sub-circuits and "rewires" around the damaged areas using appropriate logic.

Texas Instruments and ITT Corporation both saw it as a way to develop complex pipelined microprocessors and re-enter a market where they were losing ground, but neither released any products.

Gene Amdahl also attempted to develop WSI as a method of making a supercomputer, starting Trilogy Systems in 1980[4][5][6] and garnering investments from Groupe Bull, Sperry Rand and Digital Equipment Corporation, who (along with others) provided an estimated $230 million in financing.

The effort was plagued by a series of disasters, including floods which delayed the construction of the plant and later ruined the clean-room interior.

After burning through about 1⁄3 of the capital with nothing to show for it, Amdahl eventually declared the idea would only work with a 99.99% yield, which wouldn't happen for 100 years.

[10] In April 2021, Cerebras announced the WSE-2, with twice the number of transistors and 100% claimed yield,[11] which is achieved by designing a system in which any manufacturing defect can be bypassed.