Yonah's execution core contains a 12-stage pipeline, forecast to eventually be able to run at a maximum frequency of 2.33–2.50 GHz.

The communication between the L2 cache and both execution cores is handled by a bus unit controller through arbitration, which reduces cache coherency traffic over the FSB, at the expense of raising the core-to-L2 latency from 10 clock cycles (in the Dothan Pentium M) to 14 clock cycles.

However some vendors (including HP) chose to disable this feature,[4][5] with others making it available through a BIOS option.

However, Intel 64 support is integrated in Yonah's successor, the mobile version of Core 2, code-named Merom.

However, Core (Yonah) did not make any further improvements to single threaded processing performance over Dothan beyond before-mentioned SSE unit enhancements, and it was still only a 32-bit architecture, which proved to be particularly limiting for its server-oriented Sossaman derivative as x86-64 operating systems and software became increasingly prevalent.

On July 27, 2006, Intel's Core 2 processors were released, which offered x86-64 compatibility and eventually displaced Yonah in production.