Zen+

This was done to improve power efficiency & reduce thermal density to allow for higher clock speeds, rather than design an entirely new floorplan for a physically smaller die (which would have been significantly more work and thus more expensive).

[8] Although conversely at the microarchitecture level, Zen+ had only minor revisions versus Zen.

[6] Known changes to the microarchitecture include improved clock speed regulation in response to workload ("Precision Boost 2"),[9] reduced cache and memory latencies (some significantly so), increased cache bandwidth, and finally improved IMC performance allowing for better DDR4 memory support (officially JEDEC rated to support up to 2933 MHz compared to just 2666 MHz on the prior Zen core),[10] and fixed many hardware bugs found on Zen 1, such as fTPM / PSP bugs on Zen 1, and SVM / SLAT bugs on Zen 1.

Zen+ also supports improvements in the per-core clocking features, based on core utilization and CPU temperatures.

[6] These changes to the core utilization, temperature, and power algorithms are branded as "Precision Boost 2" and "XFR2" ("eXtended Frequency Range 2"), evolutions of the first-generation technologies in Zen.