In 2020, Samsung and TSMC entered volume production of "5 nm" chips, manufactured for companies including Apple, Huawei, Mediatek, Qualcomm and Marvell.
[4] In real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.
In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.
[8][9] In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.
The fabricated test chips were not fully functional devices, but rather are to evaluate patterning of interconnect layers.
[18] In April 2019, TSMC announced that their "5 nm" process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers.
[29][30][needs update] In December 2021, TSMC announced a new member of its "5 nm" process family designed for HPC applications: N4X.
The process featured optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors.
[38] On 26 August 2024 IBM introduced their Telum II processor, based on Samsung's 5 nm process.
As of 2023[update], TSMC has started producing chips for select customers, while Samsung and Intel have plans for 2024.