The Opteron CPUs feature a cache-coherent HyperTransport (ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets.
The HyperTransport bus is also distance restricted and does not permit off-system interconnect.
As far as the Opterons are concerned they are in a five-way system and this is the basic Horus node (as called 'quad').
By building the CPUs around the Horus chip with 12-bit lanes running at 3125 MHz with InfiniBand technology (8b/10b encoding), this system has an effective internal speed of 30 Gbit/s.
Dual and future quad-core chips will also be supported, allowing a single system to scale to over a hundred processing cores.