Ada Lovelace (microarchitecture)

It is named after the 19th century English mathematician Ada Lovelace,[2] one of the first computer programmers.

[14] A new stage in the ray tracing pipeline called Shader Execution Reordering (SER) is added in the Lovelace architecture which Nvidia claims provides a 2x performance improvement in ray tracing workloads.

[6] Lovelace's new fourth-generation Tensor cores enable the AI technology used in DLSS 3's frame generation techniques.

[16] Increased power efficiency can be attributed in part to the smaller fabrication node used by the Lovelace architecture.

[19] NVENC AV1 hardware encoding with support for up to 8K resolution at 60FPS in 10-bit color is added, enabling higher video fidelity at lower bit rates compared to the H.264 and H.265 codecs.

AMD's competing RDNA 3 architecture released just two months after Lovelace included DisplayPort 2.1.