AVX uses sixteen YMM registers to perform a single instruction on multiple pieces of data (see SIMD).
The legacy SSE instructions can still be utilized via the VEX prefix to operate on the lower 128 bits of the YMM registers.
AVX introduces a three-operand SIMD instruction format called VEX coding scheme, where the destination register is distinct from the two source operands.
Issues regarding compatibility between future Intel and AMD processors are discussed under XOP instruction set.
AVX2 makes the following additions: Sometimes three-operand fused multiply-accumulate (FMA3) extension is considered part of AVX2, as it was introduced by Intel in the same processor microarchitecture.
The ER, PF, 4VNNIW and 4FMAPS instruction set extensions are currently only implemented in Intel computing coprocessors.
In early 2022, Intel began disabling in silicon (fusing off) AVX-512 in Alder Lake microprocessors to prevent customers from enabling AVX-512.
It addresses several issues of AVX-512, in particular that it is split into too many parts[39] (20 feature flags) and that it makes 512-bit vectors mandatory to support.
[41] The first and "early" version of AVX10, notated AVX10.1, will not introduce any instructions or encoding features beyond what is already in AVX-512 (specifically, in Intel Sapphire Rapids: AVX-512F, CD, VL, DQ, BW, IFMA, VBMI, VBMI2, BITALG, VNNI, GFNI, VPOPCNTDQ, VPCLMULQDQ, VAES, BF16, FP16).
It is not focused on vector computation, but provides RISC-like extensions to the x86-64 architecture by doubling the number of general-purpose registers to 32 and introducing three-operand instruction formats.
Some Intel processors have provisions to reduce the Turbo Boost frequency limit when such instructions are being executed.
This reduction happens even if the CPU hasn't reached its thermal and power consumption limits.
Downclocking means that using AVX in a mixed workload with an Intel processor can incur a frequency penalty.
[69] On supported and unlocked variants of processors that down-clock, the clock ratio reduction offsets (typically called AVX and AVX-512 offsets) are adjustable and may be turned off entirely (set to 0x) via Intel's Overclocking / Tuning utility or in BIOS if supported there.