Alpha 21264
The Alpha 21264 is a RISC microprocessor developed by Digital Equipment Corporation launched on 19 October 1998.
This scheme was used as it reduced the number of write and read ports required to serve operands and receive results, thus reducing the physical size of the register file, enabling the microprocessor to operate at higher clock frequencies.
Writes to any of the register files thus have to be synchronized, which required a clock cycle to complete, negatively impacting performance by one percent.
Firstly, the higher clock frequency achievable offset the loss.
Secondly, the logic responsible for instruction issue avoided creating situations where the register file had to be synchronized by issuing instructions that were not dependent on data held in other register file where possible.
The D-cache is dual-ported by transferring data on both the rising and falling edges of the clock signal.
This method of dual-porting enabled any combination of reads or writes to the cache every processor cycle.
It is controlled by the microprocessor and is implemented by synchronous static random access memory (SSRAM) chips that operate at two thirds, half, one-third or one-fourth the internal clock frequency, or 133 to 333 MHz at 500 MHz.
The algorithm was developed by Scott McFarling at Digital's Western Research Laboratory (WRL) and was described in a 1993 paper.
The local predictor is a two-level table which records the history of individual branches.
The external interface consisted of a bidirectional 64-bit double data rate (DDR) data bus and two 15-bit unidirectional time-multiplexed address and control buses, one for signals originating from the Alpha 21264 and one for signals originating from the system.
The logic consisted of approximately six million transistors, with the rest contained in the caches and branch history tables.
The Alpha 21264 was packaged in a 587-pin ceramic interstitial pin grid array (IPGA).
Slot B was originally developed to be used by AMD's Athlon as well, so that API could obtain materials for the Slot B at commodity prices in order to reduce the cost of the Alpha 21264 to gain a wider market share.
It had a die size of 125 mm², a third smaller than the Alpha 21264A, and used a 1.7 V power supply.
It was sampled in early 2000 and achieved a maximum clock frequency of 1.25 GHz.
In September 1998, Samsung announced they would fabricate a variant of the Alpha 21264B in a 0.18 μm fully depleted silicon-on-insulator (SOI) process with copper interconnects that was capable of achieving a clock frequency of 1.5 GHz.
It was fabricated by IBM in a 0.18 μm CMOS process with seven levels of copper interconnect and low-K dielectric.
It was packaged in a 675-pad flip-chip ceramic land grid array (CLGA) measuring 49.53 by 49.53 mm.
The Alpha 21264E, code-named EV68E, was a cancelled derivative developed by Samsung first announced on 10 October 2000 at Microprocessor Forum 2000 slated for introduction at around mid-2001.
Improvements were a higher operating frequency of 1.25 GHz and the addition of an on-die 1.85 MB secondary cache.
Digital and Advanced Micro Devices (AMD) both developed chipsets for the Alpha 21264.
The D-chip is the DRAM controller, implementing access to/from the CPUs, and to/from the P-chip.
The 21272 and 21274 were used extensively by Digital, Compaq and Hewlett Packard in their entry-level to mid-range AlphaServers and in all models of the AlphaStation.
