Chip RAM is shared between the central processing unit (CPU) and the Amiga's dedicated chipset (hence the name).
Under the Amiga architecture, the direct memory access (DMA) controller is integrated into the Agnus (Alice on AGA models) chip.
The later AGA systems use a 32-bit data bus controlled by the Alice coprocessor (replacing Agnus) and 32-bit RAM.
As a result, chipset RAM bandwidth is increased fourfold compared to the earlier 16-bit design.
This improves execution speed, as CPU cycles are never blocked even when the custom chipset is simultaneously accessing Chip RAM.
Numerous budget trapdoor expansions[5] for the 500 extended this "controllerless" concept to up to 1.8 MB slow RAM (requiring a Gary adapter for addressing).