PowerVia has demonstrated significant benefits, including a 6% increase in operating frequency, 30% reduction in power loss, and more compact designs with improved density.
[1] Intel's Blue Sky Creek test chip demonstrated the benefits of this approach, showing over 90% cell utilization and potential cost reduction.
Instead, they will focus on other enhancements, such as the NanoFlex technology, which allows for greater optimization of performance, power, and area (PPA) through flexible cell design.
TSMC claims that A16 can achieve a 10% higher clock speed or a 15% to 20% decrease in power consumption compared to the N2P node, while also increasing chip density by up to 10%.
[4] The process of creating BPD-enabled chips involves additional steps, such as the creation of TSVs and the handling of wafers with interconnects on both sides.
[1] Intel plans to integrate BPD with its RibbonFET transistors in upcoming process nodes, targeting production readiness in the first half of 2024.
Samsung aims to apply BPD to its 1.4-nanometer process by 2027, focusing on reducing wafer area consumption and improving power transmission.