The chip integrates 128 channels with low-noise charge-sensitive pre-amplifiers and shapers.
Four adjacent comparator channels are being ORed and brought off chip via LVDS drivers.
Either the shaper or comparator output is sampled with the LHC bunch-crossing frequency of 40 MHz into an analog pipeline.
A binary readout mode operates at up to 80 MHz output rate on two ports.
For testability and calibration purposes, a charge injector with adjustable pulse height is implemented.