Cache inclusion policy

[1][2] Consider an example of a two level cache hierarchy where L2 can be inclusive, exclusive or NINE of L1.

It will be a miss in both L1 and L2 and hence the block is brought into both L1 and L2 from the main memory as shown in (b).

Now, assume the processor issues a read Y request which is a miss in both L1 and L2.

All reference information from L1 is passed to L2 so that it can update its replacement bits.

It will be a miss in both L1 and L2 and hence the block is brought into L1 from the main memory as shown in (b).

If this causes a block to be evicted from L1, there is no involvement of L2, which is the same as in the case of inclusive policy.

Now, if there is an eviction from L2, unlike inclusive policy, there is no back invalidation.

It will be a miss in both L1 and L2 and hence the block is brought into both L1 and L2 from the main memory as shown in (b).

This implies a shorter miss latency for an inclusive cache compared to exclusive and NINE.

Although the exclusive cache has more unique memory capacity, it uses more bandwidth since it suffers from a higher rate of filling of new blocks (equal to the rate of higher level cache's misses) as compared to NINE cache which is filled with a new block only when it suffers a miss.

Therefore, assessment of cost relative to benefit needs to be done while exploiting the choice between Inclusive, Exclusive and NINE caches.

Value Inclusion: It is not necessary for a block to have the same data values when it is cached in both higher and lower level caches even though inclusion is maintained.

[1] This depends on the write policy in use, as write back policy does not notify the lower level cache of the changes made to the block in higher level cache.