Camera Link

It was designed for the purpose of standardizing scientific and industrial video products including cameras, cables and frame grabbers.

The standard is maintained and administered by the Automated Imaging Association or AIA, the global machine vision industry's trade group.

Typically a 7× clock must be generated by a PLL or SERDES block in order to transmit or receive the serialized video.

[1][2][3] The cable used is a MDR ("Mini D Ribbon") 26-pin Male Plug Connector, optimized by 3M for the LVDS signal.

At the maximum chipset operating frequency (85 MHz), the base configuration yields a video data throughput of 2.04 Gbit/s (255 MB/s).

The Camera Link specification includes higher-bandwidth configurations that provide additional video data paths over a second connector/cable.

Data words start in the middle of the high phase of the clock, and the most significant bit is transmitted first.

[6] The bits of pixel values are not assigned to serial transmitters in order, but are permutated in a complicated way, as shown in the following figure.

The upper half of this figure is only relevant for the Medium and Full configurations which require two physical interfaces and two cables.

To the left of the transceivers, the list of pixel data bits transmitted over that Channel Link is printed, from LSB to MSB.

The standard committee adopted version 1.2 in January 2007, introducing mini SDR ("Shrunk D Ribbon") connectors (SDR-26) and power over Camera Link (POCL).