Wishbone (computer bus)

All signals are synchronous to a single clock but some slave responses must be generated combinatorially for maximum performance.

But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.

To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of prior art, to prove its concepts are in the public domain.

A device does not conform to the Wishbone specification unless it includes a data sheet that describes what it does, bus width, utilization, etc.

In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.