Powerpoint material accompanying an STI presentation given by Dr Peter Hofstee], includes a photograph of the DD2 Cell die overdrawn with functional unit boundaries which are also captioned by name, which reveals the breakdown of silicon area by function unit as follows: Additional details concerning the internal SPE implementation have been disclosed by IBM engineers, including Peter Hofstee, IBM's chief architect of the synergistic processing element, in a scholarly IEEE publication.
Understanding the limitations of the restrictive two pipeline design is one of the key concepts a programmer must grasp to write efficient SPU code at the lowest level of abstraction.
As tested by IBM under a heavy transformation and lighting workload [average IPC of 1.4], the performance profile of this implementation for a single SPU processor is qualified as follows: The entry for 2.0 GHz operation at 0.9 V represents a low power configuration.
As a general rule in CMOS circuits, power dissipation rises in a rough relationship to V2F, the square of the voltage times the operating frequency.
These figures show the part is capable of running above 5 GHz under test lab conditions—though at a die temperature too hot for standard commercial configurations.
The first Cell processors made commercially available were rated by IBM to run at 3.2 GHz, an operating speed where this chart suggests a SPU die temperature in a comfortable vicinity of 30 degrees.
IBM has publicly announced their intention to implement Cell on a future technology below the 90 nm node to improve power consumption.
This version was not yet the long-rumoured "Cell+" with enhanced Double Precision floating point performance, which first saw the light of day mid-2008 in the Roadrunner supercomputer in the form of QS22 PowerXCell blades.
Although IBM talked about and even showed higher-clocked Cells before, clock speed has remained constant at 3.2 GHz, even for the double precision enabled "Cell+" of the Roadrunner.