The contamination delay only specifies that the output rises (or falls) to 50% of the voltage level for a logic high.
The determination of the contamination delay of a combined circuit requires identifying the shortest path of contamination delays from input to output and by adding each tcd time along this path.
For a sequential circuit such as two D-flip flops connected in series, the contamination delay of the first flip-flop must be factored in to avoid violating the hold-time constraint of the second flip-flop receiving the output from the first flip flop.
Every path from an input to an output can be characterized with a particular contamination delay.
Well-balanced circuits will have similar speeds for all paths through a combinational stage, so the minimum propagation time is close to the maximum.