It is similar to direct memory access (DMA) for allowing I/O controllers to read or write RAM without CPU intervention.
In older references, the term is also used to describe traditional DMA systems where the CPU stops during memory transfers.
In this case the device is stealing cycles from the CPU, so it is the opposite sense of the more modern usage.
This was the case for the Motorola 6800 and MOS 6502 systems due to a design feature which meant the CPU only accessed memory every other clock cycle.
Cycle stealing is difficult to achieve in modern systems due to many factors such as pipelining, where pre-fetch and concurrent elements are constantly accessing memory, leaving few predictable idle times to sneak in memory access.
The IBM 1130's "cycle steal" is really DMA because the CPU clock is stopped during memory access.
[1] Cycle stealing has been the cause of major performance degradation on machine such as the Sinclair QL, where, for economy reasons, the video RAM was not dual access.