[4] Just a month later in February 2001, Cyrix III chips based on the Samuel 2 core were announced.

VIA planned to release a later version of the chip, code-named Ezra/C5C with a 0.13 micron process and speeds of 750 MHz up to possibly 1 GHz.

[7] When the chip reached reviewers, the weighted integer/floating-point performance was found to be fairly low compared to the competition.

[9][10] VIA dropped the criticized P-Rating with new processors based on the Samuel core, in favor of simply distinguishing them by their actual clock speed.

The Centaur Technology team added an on-die 64 KiB L2 cache and moved to a 150 nm manufacturing process.

These changes improved per-clock performance, reduced power demands, and increased clock speed scalability.