The Firefly was an asymmetric multiprocessor specialized racked computer as only one of the microprocessors had access to a Q-Bus interface that implemented the I/O subsystem.
The primary processor board contained a microprocessor, its floating-point coprocessor and cache, and the Q-Bus control logic.
The secondary processor boards each contained two microprocessors, their floating-point coprocessors and caches.
The original Firefly processor boards used the MicroVAX 78032 microprocessor and MicroVAX 78132 floating-point coprocessor, but later Firefly systems used the faster CVAX 78034 microprocessors, CVAX Floating Point Chips (floating-point coprocessors).
Processors in the Firefly communicated with the main memory through their individual caches and over the MBus.
These controllers operated by checking a work queue set up in the memory using DMA, providing fully symmetric access to the display hardware by all processors.
Sixty times per second, the MDC wrote to the memory the position of the mouse and an unencoded bitmap representing the state of the keyboard.
The Stanford V (operating system) also supported Firefly in a configuration with one CVAX and four Microvax-II CPUs in a BA123 chassis and QVSS?VCB01 graphics.