The company invested an estimated $1 billion in the development of the 9000, in spite of considerable in-company concern about the concept in the era of rapidly improving RISC performance.
The PDP-11 was released in 1970 and continued strong sales that would ultimately reach 600,000 machines, while their newly introduced VAX-11 picked up where the PDP ended and was beginning to make major inroads to IBM's midrange market.
DEC also introduced their famous VT series computer terminals and a wide variety of other popular peripherals that all generated significant cashflow.
Best known among these was the Rainbow 100, which aimed to offer the ability to run both MS-DOS and CP/M programs, but instead demonstrated itself incapable of doing either very well while costing about as much as buying two separate machines.
This was a stark contrast to the Unibus standard of the PDP and earlier VAX machines, which had a thriving market of 3rd party products.
These would be built onto a number of circuit boards, which would then be wire wrapped together on a backplane to produce the central processing unit (CPU).
VLSI ICs could hold hundreds of thousands or millions of transistors, enough to implement an entire VAX system on a single chip.
At that time, CMOS fabrication typically produced slower ICs than the competing emitter-coupled logic (ECL) system.
A related ECL issue was inter-chip wiring proliferation proportional to the massive pin count increase required by modern machines’ address space growth.
Trilogy's developments included a new inter-chip connection system using copper conductors embedded in polyimide insulation to produce a thin-film with extremely dense wiring.
[11] In 1984, DEC licensed parts of Trilogy's technologies and began development of practical versions of these concepts at their Hudson Fab.
Trilogy's wiring technologies were used to create card-sized "multi-chip units" (MCUs) working together like earlier multi-card CPU designs.
[12] Initially, the system required water cooling to meet its performance goals, leading to the codename Aquarius, the water-bearer.
IBM would ultimately generate roughly $14 billion in annual revenue from the line, which was more than DEC's entire company income.
[14] DEC had initially been sceptical of RISC,[15] believing it worked on trivial five-line programs but would not be successful in the transaction processing field.
This opinion was turned upside down in 1986 when an experimental RISC developed at DEC's Western Research Lab was compared head-to-head with the latest VAX 8800 and outperformed it 2-to-1.
[16] Dave Cutler, in charge of the PRISM design, then began to develop a high-end machine using it, immediately leading to fighting with the Aridus group who saw them as stepping on "their turf.
Bob Supnik claims that it was clear to senior technical people as early as 1987 that the next generation of CMOS chips, the NVAX, would perform as well as the 9000 by 1988, even though the 9000 was not slated to launch until 1989.
[14] There are several quotes by prominent engineers on the NVAX project that describe Olsen's unwillingness to kill the 9000 even after being told point-blank that it would not be competitive by the early 1990s,[14] and his outright rejection that such a thing was even possible.
The unlikely outcome of this was that all of the RISC projects were instead killed off[19] with the exception of some ongoing work at the Hudson Fab on a low-end PRISM.
[14] In February 1991, they announced a low-end version, the Model 110 at $920,000, appealing to customers looking for CPU power without the need for extensive storage or other options.
[23] In October 1991, DEC announced that the division would be reorganized as the Production System Business Unit, along with cuts on the prices of the current 9000 models of 30%, and 38% on its server software.
[24] Adding to the woes, in early 1992 it was reported that installed systems had begun to suffer a series of hardware failures that appeared to start in the second half of 1991.
[27] The V-box implementation comprised 25 Motorola Macrocell Array III (MCA3) devices spread over three multichip units (MCUs), which resided on the planar module.
From high-level behavioral and register-transfer level sources, approximately 93% of the CPU scalar and vector units, over 700,000 gates, were synthesized.
In addition to logic gate creation, SID took the design to the wiring level, allocating loads to nets and providing parameters for place and route CAD tools.