Delay-insensitive minterm synthesis

Within digital electronics, the DIMS (delay-insensitive minterm synthesis) system[1] is an asynchronous design methodology making the least possible timing assumptions.

Assuming only the quasi-delay-insensitive delay model the generated designs need little if any timing hazard testing.

The construction of DIMS logic gates comprises generating every possible minterm using a row of C-elements and then gathering the outputs of these using OR gates which generate the true and false output signals.

The acknowledge from the forward stage is inverted and passed to the C-elements to allow them to reset once the computation has completed.

Other asynchronous latches provide a higher data capacity and levels of decoupling.