In lower power systems, Hierarchical Value Cache refers to the hierarchical arrangement of Value Caches (VCs) in such a fashion that lower level VCs observe higher hit-rates, but undergo more switching activity on VC hits.
This architecture suffers from high area overhead, but reduces the bus switching activity.
The cache in HUVC in managed by LRU policy, with each VC storing 32-bit values.
However, it would require complicated logic to map VC indexes to bus values.
Except the case of first level, all VCs in HCVC store partial data values only.