Power consumption is becoming increasingly important for both embedded, mobile computing and high-performance systems.
A mix of both of these techniques produce optimal result.Value cache encoding is a scheme which is used to reduce power consumption in off chip data bus.
However, once the width of the data (that needs to be transmitted) has been reduced, we can also expect a reduction (in general) on the average bit switching activity per transfer.
In addition, this switching activity can be further reduced by using well-known bus encoding schemes in conjunction with our strategy The receiver side runs the same placement and replacement policy for the VC as the sender.
The receiver, on the other hand, fetches the value of the actual data (100 in this case) from location 5 of its VC.
Finally, in Transaction #4, we want to send the data item D having a value 200 to the memory (i.e., a write request).
Consequently, the index to the cached copy (present in the VC) of value 200 is used to complete Transaction #4 but in the reverse direction.
That is, our approach can be made to work in an environment where multiple devices are communicating over a shared (power-hungry) data bus.Obviously, in this case, among other things, we would need a coherence mechanism (the discussion of which is beyond the scope of this paper).
A drawback of our strategy is the extra space needed by two value caches (one on-chip and the other off-chip).
As will be presented in the experimental results section, even a small VC (128 entries) generates reasonably good energy behavior; so, we can expect that the space overhead due to our optimization will not be excessive.