Originally developed as the processor for a telephone switch, it was later used as the basis for a minicomputer and a number of products for their mainframe line.
[citation needed] Armed with huge amounts of performance data, IBM was able to demonstrate that the simple design was able to easily outperform even the most powerful classic CPU designs, while at the same time producing machine code that was only marginally larger than the heavily optimized CISC instructions.
This demonstrated the value of the RISC concept, and all of IBM's future systems were based on the principles developed during the 801 project.
[1] This would require a significant advance in performance; their current top-of-the-line machine, the IBM System/370 Model 168 of late 1972, offered about 3 MIPS.
[2] The group working on this project at the Thomas J. Watson Research Center, including John Cocke, designed a processor for this purpose.
[1] The telephone switch project was canceled in 1975, but the team had made considerable progress on the concept and in October IBM decided to continue it as a general-purpose design.
IBM had collected enormous amounts of statistical data on the performance of real-world workloads on their machines and this data demonstrated that over half the time in a typical program was spent performing only five instructions: load value from memory, store value to memory, adding fixed-point numbers, comparing fixed-point numbers, and branching based on the result of those comparisons.
[4] Microcode allowed a simple processor to offer many instructions, which had been used by the designers to implement a wide variety of addressing modes.
That ensured that the machine code generated by the compiler would run as fast as possible on the entire lineup.
For instance, adding two numbers from memory would require two load-to-register instructions, a register-to-register add, and then a store-to-memory.
A derivative of the 801 architecture with 32-bit addressing named Iliad was intended to serve as the primary processor of the unsuccessful Fort Knox midrange system project.
The larger instruction word also allowed the number of registers to be increased from sixteen to thirty-two, a change that had been obvious from the examination of 801 code.
[13] Other desirable additions include instructions for working with string data that was encoded in "packed" format with several characters in a single memory word, and additions for working with binary-coded decimal, including an adder that could carry across four-bit decimal numbers.
This was due to the compiler making RISC-like decisions about how the generated code uses the processor registers, thereby optimizing out as many memory accesses as possible.
The PL.8 compiler was much more aggressive about avoiding loads and saves, thereby resulting in higher performance even on a CISC processor.
[14] In the early 1980s, the lessons learned on the 801 were combined with those from the IBM Advanced Computer Systems project, resulting in an experimental processor called "Cheetah".