Intel 5-level paging

[1]: 11  It extends the size of virtual addresses from 48 bits to 57 bits by adding an additional level to x86-64's multilevel page tables, increasing the addressable virtual memory from 256 TiB to 128 PiB.

[5] Adding another level of indirection makes page table "walks" longer.

[8] In practice this cost is greatly mitigated by caches such as the translation lookaside buffer (TLB).

[12] Support for the extension was submitted as a set of patches to the Linux kernel on 8 December 2016.

[14] This is because, although Linux abstracts the details of the page tables, it still depends on having a number of levels in its own representation.

[16] Windows 10 and 11 with server versions also support this extension in their latest updates, where it is provided by a separate kernel image called ntkrla57.exe.