It builds on the channelization and per channel flow control features of SPI-4.2, while reducing the number of integrated circuit (chip) I/O pins by using high speed SerDes technology.
Bundles of serial links create a logical connection between components with multiple channels, backpressure capability, and data-integrity protection to boost the performance of communications equipment.
Interlaken manages speeds of up to 6 Gbit/s per pin (lane) and large numbers of lanes can form an Interlaken interface.
It was designed to handle high-speed (10 Gigabit Ethernet, 100 Gigabit Ethernet and beyond) computer network connections.
[citation needed] Xilinx and Intel have both developed FPGAs that have Interlaken hard IP built in.