LPDDR
Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) that consumes less power than other random access memory designs and is thus targeted for mobile computing devices such as laptop computers and smartphones.
As with standard SDRAM, most generations double the internal fetch size and external transfer speed.
[3] In 2009, the standards group JEDEC published JESD209-2, which defined a more dramatically revised low-power DDR interface.
[4][5] It is not compatible with either DDR1 or DDR2 SDRAM, but can accommodate any one of: Low-power states are similar to basic LPDDR, with some additional partial array refresh options.
Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit double data rate CA bus.
The commands are similar to those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes: Column address bit C0 is never transferred, and is assumed to be zero.
LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM.
Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command.
Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array.
LPDDR3 achieves a data rate of 1600 MT/s and utilizes key new technologies: write-leveling and command/address training,[9] optional on-die termination (ODT), and low-I/O capacitance.
On 14 March 2012, JEDEC hosted a conference to explore how future mobile device requirements will drive upcoming standards like LPDDR4.
Since the clock frequency is higher and the minimum burst length longer than earlier standards, control signals can be more highly multiplexed without the command/address bus becoming a bottleneck.
The CAS-2 command is used as the second half of all commands that perform a transfer across the data bus, and provides low-order column address bits: The burst length can be configured to be 16, 32, or dynamically selectable by the BL bit of read and write operations.
(An alternative usage, where DMI is used to limit the number of data lines which toggle on each transfer to at most 4, minimises crosstalk.
[22]: 11 LPDDR4X is identical to LPDDR4 except additional power is saved by reducing the I/O voltage (Vddq) from 1.1 V to 0.6 V. On 9 January 2017, SK Hynix announced 8 and 16 GB LPDDR4X packages.
LPDDR5 introduces the following changes:[27] AMD Van Gogh, Intel Tiger Lake, Apple silicon (M1 Pro, M1 Max, M1 Ultra, M2 and A16 Bionic), Huawei Kirin 9000 and Snapdragon 888 memory controllers support LPDDR5.
As with LPDDR4, writes must start at a multiple-of-16 address with B0–B3 zero, but reads may request a burst be transferred in a different order by specifying a non-zero value for B3.
Instead, its primary function is to prepare the DRAM to synchronize with the imminent start of the high-speed WCK clock.
On 28 July 2021, JEDEC published the JESD209-5B, Standard for Low Power Double Data Rate 5/5X (LPDDR5/5X)[30] with the following changes: On 9 November 2021, Samsung announced that the company has developed the industry's first LPDDR5X DRAM.
[33] On 25 January 2023 SK Hynix announced "Low Power Double Data Rate 5 Turbo" (LPDDR5T) chips with a bandwidth of 9.6 Gbit/s.
This is achieved through a new 12 nm process that allows the chips to be more efficient while also being small enough to fit capacities of up to 32 GB in a single package.
[36] On 16 July 2024 Samsung has completed validation of the industry's fastest LPDDR5X DRAM, capable of operating at speeds up to 10.7Gbit/s, for use in MediaTek's upcoming flagship Dimensity 9400 SoC.
