XDR DRAM

XDR was designed to be effective in small, high-bandwidth consumer systems, high-performance memory applications, and high-end GPUs.

It eliminates the unusually high latency problems that plagued early forms of RDRAM.

Also, XDR DRAM has heavy emphasis on per-pin bandwidth, which can benefit further cost control on PCB production.

In addition, each chip has a low-speed serial bus used to determine its capabilities and configure its interface.

All single-ended lines are active-low; an asserted signal or logical 1 is represented by a low voltage.

The request bus operates at double data rate relative to the clock input.

This operates equivalently to standard SDRAM's activate command, specifying a row address to be loaded into the bank's sense amplifier array.

In this case, the SR1..0 bits specify the half or quarter of the row to activate, and following read/write commands' column addresses are required to be limited to that portion.

Just as with other forms of SDRAM, the DRAM controller is responsible for ensuring that the data bus is not scheduled for use in both directions at the same time.

Unlike conventional SDRAM, there is no provision for choosing the order in which the data is supplied within a burst.

Even when multiple devices are connected in parallel, a mask byte can always be found when the bus is at most 128 bits wide.

Three subcommands start and stop output driver calibration (which must be performed periodically, every 100 ms).

Commands sent by the controller over the CMD line include an address which must match the chip ID field.

Normally, the CMD line is left high (logic 0) and SCK pulses have no effect.