Logic level

Logic levels are usually represented by the voltage difference between the signal and ground, although other standards exist.

Occasionally a logic design is simplified by inverting the choice of active level (see De Morgan's laws).

Logic families such as TTL can sink more current than they can source, so fanout and noise immunity increase.

However, few logic circuits can detect such a condition, and most devices will interpret the signal simply as high or low in an undefined or device-specific manner.

Interconnecting any two logic families often required special techniques such as additional pull-up resistors or purpose-built interface circuits known as level shifters.

This problem was solved by the invention of the 74HCT family of devices that uses CMOS technology but TTL input logic levels.

It means that an input is undefined, or an output signal may be chosen for implementation convenience (see Karnaugh map § Don't cares).

The standard includes strong and weakly driven signals, high impedance and unknown and uninitialized states.

Storing n bits in one cell requires the device to reliably distinguish 2n distinct voltage levels.

Examples include alternate mark inversion and 4B3T from telecommunications, and pulse-amplitude modulation variants used by Ethernet over twisted pair.