Logic synthesis

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool.

[1] Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs.

In the early days, logic design involved manipulating the truth table representations as Karnaugh maps.

[needs update] Another area of early research was in state minimization and encoding of finite-state machines (FSMs), a task that was the bane of designers.

Work on LSS and the Yorktown Silicon Compiler spurred rapid research progress in logic synthesis in the 1980s.

Within a decade, the technology migrated to commercial logic synthesis products offered by electronic design automation companies.

Their synthesis tools are Synopsys Design Compiler, Cadence First Encounter and Siemens Precision RTL.

These tools automatically synthesize circuits specified using high-level languages, like ANSI C/C++ or SystemC, to a register transfer level (RTL) specification, which can be used as input to a gate-level logic synthesis flow.