Metastability (electronics)

As a result, the circuit can act in unpredictable ways, and may lead to a system failure, sometimes referred to as a "glitch".

[4] Metastable states are avoidable in fully synchronous systems when the input setup and hold time requirements on flip-flops are satisfied.

A simple example of metastability can be found in an SR NOR latch, when both Set and Reset inputs are true (R=1 and S=1) and then both transition to false (R=0 and S=0) at about the same time.

Arbiters are used in asynchronous circuits to order computational activities for shared resources to prevent concurrent incorrect operations.

[6] Synchronizer circuits are used to reduce the likelihood of metastability when receiving an asynchronous input or when transferring signals between different clock domains.

[8] Although metastability is well understood and architectural techniques to control it are known, it persists as a failure mode in equipment.

Proper testing for metastability frequently employs clocks of slightly different frequencies and ensuring correct circuit operation.

Figure 1. An illustration of metastability in a synchronizer , where data crosses between clock domains. In the worst case, depending on timing, the metastable condition at D s can propagate to D out and through the following logic into more of the system, causing undefined and inconsistent behavior.
Figure 2. The Set–Reset NOR latch example
Figure 3. This 4-bit shift register acts as a synchronizer. As the unsynchronized input data0 travels though each flip-flop stage, its likelihood of remaining metastable decreases dramatically, since almost an entire clock cycle is available during each stage for resolving possible metastability from the prior stage.