Rigel (microprocessor)

It was introduced on 11 July 1989 with the introduction of the VAX 6000 Model 400, the first system to feature the chip set.

It has a six-stage microinstruction pipeline and 64-entry fully associative translation look-aside buffer.

The chip set was fabricated by DEC in their second-generation complementary metal–oxide–semiconductor (CMOS) process, CMOS-2.

The process had a 1.5 μm minimum feature size and two levels of aluminium interconnect.

Mariah was a revised version of the Rigel chip set fabricated by DEC in their 1 μm CMOS-3 process, with higher clock frequencies between 55 and 71 MHz.