[1] The term rank was created and defined by JEDEC, the memory industry standards group.
On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit-wide data bus (72 bits wide on DIMMs that support ECC).
The electrical connections between the memory controller and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks).
[citation needed] Predating the term rank (sometimes also called row) is the use of single-sided and double-sided modules, especially with SIMMs.
[2][3] A Multi-Ranked Buffered DIMM (MR-DIMM) allows both ranks to be accessed simultaneously by the memory controller, and is supported by AMD, Google, Microsoft, JEDEC, and Intel.