Memory geometry

Modules with the number of RAM chips equal to some power of two do not support memory error detection or correction.

This designates the technology, and classification of the modules, for instance whether it is DDR2, or DDR3, and whether it is suitable for desktops, or for servers.

By consulting the documentation of your motherboard, or reading the labels on the board itself, you can determine the underlying logical structure of the slots.

With AMD's release of the Opteron, which integrated the memory controller into the CPU, NUMA systems that share more than one memory controller in a single system have become common in applications that require the power of more than the common desktop.

[citation needed] Channels are the highest-level structure at the local memory controller level.

In contrast, banks, while similar from a logical perspective to ranks, are implemented quite differently in physical hardware.

Because memory bus width is usually larger than the number of chips, most chips are designed to have width, meaning that they are divided into equal parts internally, and when one address "depth" is called up, instead of returning just one value, more than one value is returned.

In addition to the depth, a second addressing dimension has been added at the chip level, banks.

[citation needed] Some measurements of modules are size, width, speed, and latency.

As noted in the memory channel part, one physical module can be made up of one or more logical ranks.

The logical features section described NUMA configurations, which can take the form of a network of memory controllers.

Various methods of specifying memory geometry can be encountered, giving different types of information.

For example, 64 would indicate a 64-bit data width, as is found on non-ECC DIMMs common in SDR and DDR1–4 families of RAM.

Example: for a memory chip with 128 Mib capacity and 8-bit wide data bus, it can be specified as: 16 Meg × 8.