To prevent this, external circuitry periodically reads each cell and rewrites it, restoring the charge on the capacitor to its original level.
Therefore, DRAM is used for the main memory in computers, video game consoles, graphics cards and applications requiring large capacities and low cost.
[needs update] The maximum time interval between refresh operations is standardized by JEDEC for each DRAM technology and is specified in the manufacturer's chip specifications.
For DDR2 SDRAM chips it is 64 ms.[11]: 20 Maximum refresh interval depends on the ratio of charge stored in the memory cell capacitors to leakage currents.
The actual persistence of readable charge values and thus data in most DRAM memory cells is much longer than the refresh interval, up to 1–10 seconds.
[12] However, transistor leakage currents vary widely between different memory cells on the same chip due to process variation.
[13] This frequent DRAM refresh consumes a third of the total power drawn by low-power electronics devices in standby mode.
Experiments show that in a typical off-the-shelf DRAM chip, only a few weak cells really require the worst-case 64 ms refresh interval,[14] and even then only at the high end of its specified temperature range.
Some experiments combine these two complementary techniques, giving correct operation at room temperature at refresh intervals of 10 seconds.
Here, RAS refresh is signaled by a unique combination of address and control wires during operationally redundant clock cycles (T-States), i.e. during instruction decode and execution when the buses may not be required.
With the advent of 64 kbit+ DRAM chips (with 256 rows), extra circuitry or logic had to be built around the refresh signal to synthesize the missing 8th bit and prevent blocks of memory contents from being lost after a few milliseconds.
In some contexts, it was possible to utilize interrupts and software to flip the 8th bit at the appropriate time and thus cover the entire range of the R register (256 rows).
Another method, perhaps more universal but also more complex in terms of hardware, was to use an 8-bit counter chip, whose output would provide the refresh RAS address instead of the R register.
Later versions and licensed work-alikes of the Z80 core remedied the non-inclusion of the 8th bit in automatic cycling, and modern CPUs have greatly expanded on such basic provisioning to provide rich all-in-one solutions for DRAM refresh.
The Williams tube has the closest similarity, since, like DRAM, it is essentially a capacitive memory in which the values stored for each bit would gradually decay unless refreshed.
Some early computers implemented atomic read–modify–write cycles (combined read and write with modify) for increment and decrement.