OpenRISC

OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles.

The first (and as of 2019[update] only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support.

[4] The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL).

Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays (FPGAs),[8][9] and there have been several commercial derivatives produced.

The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout.

By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began a crowdfunding project to build a cost-efficient application-specific integrated circuit (ASIC) to get improved performance.

For example, Stefan Wallentowitz[17] and his team at the Institute for Integrated Systems at the Technische Universität München have used OpenRISC in research into multi-core processor architectures.

[22] Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in JavaScript, running Linux with X Window System and Wayland support.

A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (see OVPsim), set up by Imperas.