In electronic low power digital synchronous circuit design, operand isolation is a technique for minimizing the energy overhead associated with redundant operations by selectively blocking the propagation of switching activity through the circuit.
[1] This technique isolates sections of the circuit (operation) from "seeing" changes on their inputs (operands) unless they are expected to respond to them.
There is some area overhead associated with this technique since the circuit designer needs to add extra circuitry, i.e. latches, at the inputs.
Also, if the latches are being added in a pipeline stage, they might change the critical path, and hence increase the propagation delay and cycle time.
In cases where the overhead is not acceptable, one can think of clock gating as an alternative method of low power design.