Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, enabling RS/6000 and eServer iSeries models of AS/400 computer servers to run on the same processor, as a step toward converging the two lines.

The Non-Cacheable (NC) Unit is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topology.

There is also a Built In Self Test function (BIST) and Performance Monitoring Unit (PMU).

These execution units can complete up to eight operations per clock (not including the BR and CR units): The pipeline stages are: The POWER4 also came in a configuration using a multi-chip module (MCM) containing four POWER4 dies in a single package, with up to 128 MB of shared L3 ECC cache per MCM.

[3] It contained 184 million transistors, measured 267 mm2, and was fabricated in a 0.13 μm SOI CMOS process with eight layers of copper interconnect.