It was introduced on 5 October 1998, debuting in the RS/6000 43P Model 260, a high-end graphics workstation.

The POWER3 was the successor of the P2SC derivative of the POWER2 and completed IBM's long-delayed transition from POWER to PowerPC, which was originally scheduled to conclude in 1995.

It competed with the Digital Equipment Corporation (DEC) Alpha 21264 and the Hewlett-Packard (HP) PA-8500.

The front end has a short pipeline, resulting in a small three-cycle branch misprediction penalty.

To reduce the number of ports required to provide data and receive results, the general purpose register file is duplicated so that there are two copies, the first supporting three integer execution units and the second supporting the two load/store units.

Compared to the PowerPC 620, there were more rename registers, which allowed more instructions to be executed out of order, improving performance.

Two of the units are identical and execute all integer instructions except for multiply and divide.

Divide and square-root instructions are executed in the same FPUs, but are assisted by specialized hardware.

After execution is completed, the instructions are held in buffers before being committed and made visible to software.

Its capacity was doubled to 64 KB, to improve the cache-hit rate; the cache was dual-ported, implemented by interleaving eight banks, to enable two loads or two stores to be performed in one cycle in certain cases; and the line-size was increased to 128-bytes.