As research and development progressed and the size of the network grew, it was determined that the internetworking design that was being used was becoming unwieldy and it did not exactly follow the layered approach of the OSI Model.
In this paradigm shift, networks are viewed as collections of systems that transmit data in small packets that work their way from origin to destination by any number of routes.
[21] The data plane is a subsystem of a network node that receives and sends packets from an interface, processes them as required by the applicable protocol, and delivers, drops, or forwards them as appropriate.
It contains processes that support operational administration, management or configuration/provisioning actions such as: More sophisticated solutions based on XML (eXtensible Markup Language) can also be included.
For example, in voice and video applications, the necessary conversion from analog-to-digital and back again at the destination along with delays introduced by the network can cause noticeable gaps that are disruptive to the users.
Only those packets that require complex processing are forwarded to the OS networking stack (the upper layer of the data plane), which performs the necessary management, signaling and control functions.
When complex algorithms such as routing or security are required, the OS networking stack forwards the packet to dedicated software components in the control plane.
These technologies, which span the breadth of hardware and software, have all been designed with the aim of maximizing speed and throughput while minimizing latency.
NPUs commonly have network-specific functions such as address lookup, pattern matching and queue management built into their microcode.
Some multicore processors integrate dedicated packet processing capabilities to provide a complete SoC (System on Chip).
They generally integrate Ethernet interfaces, crypto-engines, pattern matching engines, hardware queues for QoS and sometimes more sophisticated functions using micro-cores.
For clearly definable and repetitive actions, creating a dedicated accelerator built directly into a semiconductor hardware solution will speed up operations when compared to software running on a general purpose processor.
[30] Initial implementations used FPGAs (field-programmable gate array) or ASICs (Application-specific Integrated Circuit), but now specific functions such as encryption and compression are built into both GPPs and NPUs as internal hardware accelerators.
[32] Being able to make decisions based on the content of individual packets enables a wide variety of new applications such as policy and charging rules function (PCRF) and Quality of Service.
DPI technologies utilize pattern matching algorithms to look inside the data payload to identify the contents of each and every packet flowing through a network device.
[34] To be able to implement operating system by-pass (fast path) architectures requires the use of specialized packet processing software such as 6WIND's 6WINDGate.
This type of software provides a suite of networking protocols that can be distributed across multiple blades, processors or cores and scale appropriately.