PowerPC G4

Besides desktop computers the PowerPC G4 was popular in embedded environments, like routers, telecom switches, imaging, media processing, avionics and military applications, where one can take full advantage of the AltiVec technology and its SMP capabilities.

The chip operates at speeds ranging from 350 to 500 MHz and contains 10.5 million transistors, manufactured using Motorola's 0.20 μm HiPerMOS6 process.

The incident generated a rift in the Apple-Motorola relationship, and reportedly caused Apple to ask IBM for assistance to get the production yields up on the Motorola 7400 series line.

Ultimately, the G4 architecture design contained a 128-bit vector processing unit labelled AltiVec by Motorola while Apple marketing referred to it as the "Velocity Engine".

Compared to Intel's x86 microprocessors at the time, this feature offered a substantial performance boost to applications designed to take advantage of the AltiVec unit.

Additionally, the 7400 has enhanced support for symmetric multiprocessing (SMP) thanks to an improved cache coherency protocol (MERSI) and a 64-bit floating point unit (FPU), derived in part from the 604 series.

The chip added the ability to use all or half of its cache as high-speed, non-cached memory mapped to the processor's physical address space as desired.

The 33-million transistor chip extended significantly the execution pipeline of 7400 (7 vs. 4 stages minimum) to reach higher clock speeds, improved instruction throughput (3 + branch vs. 2 + branch per cycle) to compensate for higher instruction latency, replaced an external L2 cache (up to 2 MB 2-way set associative, 64-bit data path) with an integrated one (256 KB 8-way set associative, 256-bit data path), supported an external L3 cache (up to 2 MB 8-way set associative, 64-bit data path), and featured many other architectural advancements.

It came with a wider, 256-bit on-chip cache path, and was fabricated in Motorola's 0.18 μm (180 nm) HiPerMOS process with copper interconnects and SOI.

With the 7447A, which introduced an integrated thermal diode as well as DFS (dynamic frequency scaling) Freescale was able to reach a slightly higher clock.

Improvements were a larger 1 MB L2 cache, a faster 200 MHz front side bus, and lower power consumption (18 W at 1.7 GHz).

PowerPC 7448 users were: In 2004, Freescale renamed the G4 core to e600 and changed its focus from general CPUs to high-end embedded SoC devices, and introduced a new naming scheme, MPC86xx.

The 7448 was to be the last pure G4 and it formed the base of the new e600 core with a seven-stage, three-issue pipeline, and a powerful branch prediction unit which handles up to sixteen instructions out-of-order.