Speeds range up to 2.5 GHz, and the core is designed to be highly configurable via the CoreNet fabric and meet the specific needs of embedded applications with features like multi-core operation and interface for auxiliary application processing units (APU).
The e5500 is based on the e500mc core and adds some new instructions introduced in the Power ISA 2.06 specification, namely some byte- and bit-level acceleration; Parity, Population count, Bit permute and Compare byte.
The FPU is taken straight from the PowerPC e600 core, which is a classic fully pipelined dual precision IEEE 754 unit running at full core speed and supports conversion between 64-bit floats and integers, effectively twice as fast as the FPU in e500mc.
Simulated models were available in July 2010, hard samples in late 2010 and full scale manufacturing the second half of 2011.
[2] e5500 powers the high-performance QorIQ P5 system on a chip (SoC) family which share the common naming scheme: "P50x0".